601.229: Computer Systems Fundamentals
You’re in the right place if you’re looking to understand computer
systems from the bottom up. We’ll start with digital design, work our
way up to a simple 4-bit CPU, and then explore RISC as well as CISC
architectures such as MIPS and x86. You’ll learn how computers actually
work, how they are programmed in assembly, and how systems software
allows us to turn these chunks of silicon into useful devices.
Catalog Description: We study the design and performance of a
variety of computer systems from simple 8-bit micro-controllers through
32-bit RISC architectures all the way to the ubiquitous x86 CISC
architecture. We’ll start from logic gates and digital circuits before
delving into arithmetic and logic units, registers, caches, memory,
stacks and procedure calls, pipelined execution, super-scalar
architectures, memory management units, etc. Along the way we’ll study
several typical instruction set architectures and review concepts such
as interrupts, hardware and software exceptions, serial and other
peripheral communications protocols, etc. A number of programming
projects, frequently done in assembly language and using various
processor simulators, round out the course.
Prerequisite(s): 601.220: Intermediate Programming.
(For some assignments, 601.226: Data Structures is also useful.)
Please read the
general course policies
and take them to heart.
Additional policies specific to this course may be posted at a later date.
There is no required text. However, it is strongly recommended that
you get yourself a text book anyway. The following two are both
excellent, but neither covers exactly what we’ll do in the course, and
both cover things that we’ll never mention.
Note that most editions will do, you don’t necessarily need the latest
and therefore most expensive one.
Neither text has a lot of detail on digital design, but we’ll try to
supplement the lectures with plenty of links to help you out.
- Projects (about 5–7): 50%
- Quizzes (about 5–7): 20%
- Final: 30%
Homework assignments are designed for you to practice certain skills
and techniques, they are not graded. If you want feedback on your
solutions, please ask in office hours.
Projects are designed to evaluate how well you’ve mastered course material.
They are graded.
Please check the individual projects for due dates and the structure your
solutions should have.
See our Piazza site for detailed submission instructions.
This is not a schedule.
It’s a “log” of what we did, roughly, in each lecture.
Don’t expect it to turn into a schedule, it won’t.
- August 31: Welcome;
- September 1: Review of independent compilation in C;
- September 4: No lecture
- September 6: Using
static to make file-scope declarations “private”;
introduction to digital signals (high/low, 0/1, true/false, etc.);
real versus ideal signals (overshoot, bouncing, propagation delay);
one-input-one-output logic gates (specifically the NOT gate);
two-input-one-output logic gates (specifically the AND and OR gates);
truth tables to describe/define gates (and to count the number of
- September 8: Symbols for NOT, AND, OR, NAND, NOR gates;
notations for boolean expressions/formulas;
boolean algebra review, including DeMorgan’s law
- September 11: Combinational circuits;
2-to-4 decoder example (truth table, circuit diagram, boolean formulas);
the half-adder example;
toward a “design process” from truth tables to circuits;
disjunctive and conjunctive normal forms (DNF, CNF);
deriving the formula for a circuit in DNF;
drawing the circuit diagram from the formula
- September 13: deriving the formula for a circuit in CNF;
some properties of circuits in normal form;
formally deriving the half-adder circuit;
note on XOR gate;
introduction to multiplexers and demultiplexers;
the 2-to-1 MUX;
deriving the 2-to-1 MUX circuit in DNF;
simplifying the circuit (just an example, don’t do this on assignments/exams
unless asked to)
- September 15: (incomplete log)
positional numeral systems
adding numbers in binary;
the full-adder circuit;
building an n-bit ripple-carry adder (and why carry-lookahead adders are
- September 18: (incomplete log) binary representation of signed integers
(sign and magnitude, one’s completent, two’s complement); subtraction by
adding two’s complement representations
- September 20: Simple NAND RS latch;
(simplified) discussion of RS latch behavior;
the hold, set, reset, and illegal inputs;
circuit to add a clock signal;
circuit to avoid illegal input;
combining the two for a D-type latch
- September 22: Review of D-type latch;
from level-triggered to edge-triggered;
(brief aside: edge-detector circuit);
D-type master-slave flip-flop using a two-phase clock;
building an n-bit register (including a LOAD line);
building an n-bit counter (some details omitted)
- missing a few lectures, sorry
- September 27: The SCRAM, an 8-bit machine (arithmetic) with a 4-bit
address space; the 16x8 memory circuit; the MAR and MBR registers to
access memory; program and data in one memory,
von Neumann or
as opposed to
“It’s all just zeros and ones!”;
the PC (program counter) register and sequential execution;
fetching an instruction from memory into the IR register.
- September 29: Quiz 1; review of memory (MAR, MBR), PC, and IR registers;
the CLU as the “brain” of the machine; inputs are the decoded instruction
(q signals) as well as the decoded time step (t signals); outputs are the
various control lines (x signals); the fetch cycle in detail; writing the
micro program for t0, t1, and t2; parallelism in the t1 step to increment
PC at the same time; mapping each micro program step to the control lines
necessary to actually “carry out” that step; micro programs for steps t3,
t4, etc. depend on actual instruction; need to “reset” the counter at the
end of every instruction.
- missing a few lectures, sorry
- October 6: Using the SCRAM assembler, disassembler, and simulator;
detailed demo using the
common features of assembly languages (line-oriented, labels).
- October 9: High-speed intro to the
MOS 6502 CPU via Michael
Steil’s Reverse Engineering the MOS 6502 CPU.
- October 11: Slowed-down intro to the
(covering only the first third of Monday’s talk);
basic 6502 programming model (A, X, Y, P, S, and PC registers);
overview of instructions (memory access, register transfers, arithmetic
and logic, control flow including conditional branches with limited range);
instructions and flags;
“Some instructions set some flags, check documentation!”;
idea of addressing modes to keep number of mnemonics low;
“Some instructions support some addressing modes, check documentation!”;
variable-length instruction encoding, 1-3 bytes;
little endian encoding for addresses in memory.
- some missing, sorry
- October 23: Tour of Peter’s mediocre solution to Project 2.
- lots missing, sorry
- November 27: Experiments to discover that accessing memory is not actually
constant time; history of CPU/RAM disparity; caches and the memory hierarchy