A Machine-Learning Approach to Analog/RF Circuit Testing

Yiorgos Makris, Yale University

The objective of this talk is to demonstrate the utility of machine learning in developing a cost-effective test solution for analog/RF circuits. I will first introduce the problem of testing analog/RF chips for manufacturing defects and the current industrial practice, which involves explicit specification measurements obtained through expensive instrumentation. I will then describe an ontogenic neural classifier that learns to separate nominal from faulty chip distributions in a low-dimensional space of inexpensive measurements. The key novelty of this classifier is that its topology is not fixed; rather, it adapts dynamically, in order to match the inherent complexity of the separation problem. Thus, it establishes separation hypersurfaces that reciprocate very well even in the presence of complex chip distributions. I will also discuss the construction of guard-bands, which provide a level-of-confidence indication and support a two-tier test method that allows exploration of the trade-off between test quality and test cost. In this method, the majority of chips are accurately classified through inexpensive measurements, while the small fraction of chips for which the decision of the classifier has a low level of confidence is re-tested through traditional specification testing. The ability of the proposed method to drastically reduce the cost of analog/RF testing without compromising its quality will be demonstrated using two example circuits, a simple switched-capacitor filter and an industrial UHF receiver front-end. In addition, the application of the neural classifier to the problem of analog specification test compaction and its potential for developing a stand-alone Built-in Self-Test (BIST) method for analog/RF circuits will be discussed.

Speaker Biography

Yiorgos Makris received the Diploma of Computer Engineering and Informatics from the University of Patras, Greece, in 1995, and the M.S. and Ph.D. degrees in Computer Engineering from the University of California, San Diego, in 1997 and 2001, respectively. He then joined Yale University where he has been instrumental in revitalizing the Computer Engineering program. He is currently an Associate Professor of Electrical Engineering and Computer Science and leads the Testable and Reliable Architectures (TRELA) Laboratory. His main research interests are in the application of machine learning and statistical analysis methods towards increasing testability, reliability, and security of analog/RF devices. He is also interested in test and reliability methods for asynchronous circuits, as well as error detection and correction methods for modern microprocessors. His research has been supported by NSF, DARPA, SRC, IBM, LSI, Intel, and TI.