The recent growth in both size and speed of FPGAs (Field Programmable Gate Arrays) have opened up tremendous opportunities for using these as spatial computing platforms in the form of hardware accelerators. However, the major obstacle to a wide adoption of these platforms is their programmability. FPGAs have traditionally been programmed using HDLs (Hardware Description Languages) a low-level, tedious and error prone process. HLL (High-level Languages) on the other hand embody a temporal execution paradigm that presupposes a central control, a central storage, control driven sequencing of operations, etc. Translating HLLs into spatial computing structures requires a radical change of the underlying computing model. In this talk I describe our experience with ROCCC (Riverside Optimizing Compiler for Configurable Computing) an on-going research project whose goal is to develop a compiler framework for translating C code to VHDL for the generation of FPGA-based hardware accelerators. ROCCC has been used on a wide variety of applications such as image and video processing, molecular dynamics, bioinformatics, data mining, cryptography, string matching etc. Observed speedup over CPUs range from one to three orders of magnitude. We are currently developing ROCCC 2.0 which builds upon the experience with the first version of ROCCC.
Speaker Biography
Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His research interests are in the fields of computer architecture, compiler optimizations and embedded systems. Lately, he has been very active in the area of compilation for FPGA-based code acceleration and reconfigurable computing. His research has been supported by NSF, DARPA and various industry sponsors. He received a B.E. in Electrical Engineering from the American University of Beirut in 1979 and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. He was on the faculty of the Department of Computer Science at Colorado State University (1989 to 2000), before that he was with the USC-Information Sciences Institute (1986 to 1989). He has served on the program committees for a number of leading conferences in this area including CASES, ISSS-CODES, DATE, HPCA, and MICRO. He is a Fellow of the IEEE.