Challenges and Solutions in Embedded Systems: IP Protection, Low Power, and QoS

Gang Qu, University of California, Los Angeles

The emergence of embedded systems has been impacting system design paradigms, design flows and tools along many dimensions. The goal of my talk is to present techniques that provide solutions to some of the most challenging problems in embedded system design. In particular, I will talk about intellectual property (IP) protection, power minimization using variable voltage and embedded system design for guaranteed quality of service (QoS).

Short time to market and cost sensitivity of the embedded systems imply a strong need for hardware and software reuse. We have developed a technique that embeds robust copyright marks to system building blocks. We impose additional author-specific constraints on the original IP specification during its creation and/or synthesis. The copyright detector checks whether a synthesized IP block satisfies the author-specific constraints. The strength of the proof of authorship is proportional to the likelihood that an arbitrary synthesis tool incidentally satisfies all the added constraints. I will present the theoretical analysis along with the developed concepts and experimental results obtained on several traditional synthesis problems.

As variable voltage systems are rapidly moving from research testbeds to commercial products (e.g. the Crusoe processor by Transmeta), the real-time OS developers are encountering the challenge of modifying traditional OS scheduling primitives for such systems. I will present a task scheduling paradigm for dynamically changing voltage to minimize the power consumption, while satisfying the system’s real-time constraints.

In the third part of my talk, I will present a two-phase design methodology that optimizes the traditional design objectives while providing guaranteed QoS. The QoS requirements will be considered in the early design stages and other design metrics (e.g., silicon area, performance, and power) will be optimized through configuring system components (CPU and cache). I will illustrate this by showing how to determine the minimal chip size to provide latency and synchronization guarantees to multimedia applications.