A computer system has a 4GBytes disk and 128MBytes of memory with the following parameters:
Register access time: negligible (zero).
Memory access time: 1 micro second
Disk access time: 10 mili second to get/put the data (including transfer time).
The system is a virtual memory system with demand paging. The operating system manages
the page table in direct access.
When we access a virtual address, if the required page is not in memory, the operating system
brings the page from the disk and restarts the operation.
There is a 20% likelihood that the page that is brought into memory replaces a dirty page that
has to be written to the disk.
Assume that the process page table is completely in memory when the process is running.
1. Assuming that the page fault rate is 99.999% (the likelihood of a virtual memory access to be
a “hit”). What is the system effective access time to memory?
2. How can we improve this virtual memory system by adding a TLB using a small array of registers?
What will be the best (lower bound) effective access time to memory that can be achieved in this
3. Going back to the system in question 1. We add a 256KBytes cache to the CPU with access
time of 100 nano second. Assume that the cache key is a virtual address.
What the cache hit ration needs to be in order for the effective access time to memory to be 500