November 18, 2008 - Walid Najjar

Title: Opportunities and Challenge of the Spatial Computing Paradigm - The Programmability Issue

Abstract:
The recent growth in both size and speed of FPGAs (Field Programmable Gate Arrays) have opened up tremendous opportunities for using these as spatial computing platforms in the form of hardware accelerators. However, the major obstacle to a wide adoption of these platforms is their programmability. FPGAs have traditionally been programmed using HDLs (Hardware Description Languages) a low-level, tedious and error prone process. HLL (High-level Languages) on the other hand embody a temporal execution paradigm that presupposes a central control, a central storage, control driven sequencing of operations, etc. Translating HLLs into spatial computing structures requires a radical change of the underlying computing model. In this talk I describe our experience with ROCCC (Riverside Optimizing Compiler for Configurable Computing) an on-going research project whose goal is to develop a compiler framework for translating C code to VHDL for the generation of FPGA-based hardware accelerators. ROCCC has been used on a wide variety of applications such as image and video processing, molecular dynamics, bioinformatics, data mining, cryptography, string matching etc. Observed speedup over CPUs range from one to three orders of magnitude. We are currently developing ROCCC 2.0 which builds upon the experience with the first version of ROCCC.